The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor configuration suitable for passively limiting an electric current, and to an implementation of the novel configuration.
To supply an electrical consumer (load device) with an electric current, the consumer is connected to a line branch of an electrical supply network via a switching device. To protect the consumer against excessive currents, particularly in the event of a short circuit, low-voltage technology uses a switching device with an isolator, for which a fuse is generally used, protecting the line branch and with a mechanical power switch having a switching time of markedly more than one millisecond (1 ms). If a plurality of consumers are operated at the same time in a line branch and a short circuit occurs in only one of these consumers, then it is greatly advantageous if the consumers not affected by the short circuit can continue to operate without fault and only the consumer affected by the short circuit is switched off. To this end, current-limiting components (limiters) connected immediately upstream of each consumer are required. Each of the current limiters reliably limit the current of the prospective short-circuit current to a predetermined, noncritical overcurrent value within a time of markedly less than 1 ms, and hence before the isolator provided for the line branch is triggered. In addition, these current-limiting components should work passively without any driving and should be able to tolerate voltages of, typically, up to 700 V and from time to time up to 1200 V which are present during current limiting. Since the power loss which then occurs in the component is very high, it would be particularly advantageous if the passive current limiter were also to reduce the current to values markedly below the predetermined overcurrent value automatically, with additional voltage uptake (intrinsically safe component).
The only commercially available passive current limiter known to the inventors is a device described by T. Hansson in a paper titled xe2x80x9cPolyethylen-Stromwxc3xa4chter fxc3xcr den Kurzschluxcex2schutzxe2x80x9d [Polyethylene current monitor for short-circuit protection], ABB Technik 4/92, pages 35-38. That device is distributed under the product name PROLIM and is based on current-dependent conductivity of the grain boundaries of the material used in the device. When the device is used relatively frequently for current limiting, however, the current saturation value at which the current is limited may be changed.
Otherwise, only active current limiters are used in general, which detect the current and limit it by active control if a predetermined maximum current value is exceeded. Such a semiconductor-based active current limiter is described in German published patent application DE 43 30 459. That device has a first semiconductor region of a predetermined conductivity type which is allocated a respective electrode on mutually remote surfaces. In the first semiconductor region, further semiconductor regions of the opposite conductivity type are formed at a distance from one another between the two electrodes. Channel regions of the first semiconductor region are formed between each of the further semiconductor regions and are oriented perpendicularly to the two surfaces of the first semiconductor region (vertical channels). A vertical flow of current between the two electrodes is routed through these channel regions and limited thereby. To control the flow of current between the two electrodes, a gate voltage is applied to the oppositely doped semiconductor regions in the first semiconductor region. The gate voltage controls the resistors in the channel regions.
It is accordingly an object of the invention to provide a semiconductor configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be used for passively limiting electric currents when a critical current value is exceeded. It is a further object of the invention to provide a current limiter device with such a semiconductor configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, an claim 1.
A semiconductor configuration, comprising:
a first electrode and a second electrode;
a first semiconductor region having a first surface formed with at least one contact region in contact with the first electrode, having a second surface in contact with the second electrode, and defining a current path between the first and second electrodes;
a second semiconductor region disposed to form a p-n junction with the first semiconductor region and an associated depletion zone;
a third semiconductor region disposed to form a p-n junction with the first semiconductor region and an associated depletion zone;
the third semiconductor region having a surface not adjoining the first semiconductor region an being insulated for charge storage charges in the third semiconductor region;
the first semiconductor region being formed with at least one channel region in the current path between the first and second electrodes and, upon attaining a predetermined saturation current between the first and second electrodes, the depletion zones of the p-n junctions pinching off the channel region and limiting the current to a value below the saturation current.
In other words, the novel semiconductor configuration is formed with:
a) a first semiconductor region, which, on a first surface, is in contact with a first electrode in at least one contact region, and is in contact with a second electrode on a second surface;
b) at least one second semiconductor region, which forms a p-n junction with the first semiconductor region;
c) at least one third semiconductor region, which forms a p-n junction with the first semiconductor region;
where
d) the third semiconductor region is insulated on its surface not adjoining the first semiconductor region, so that electrical charges can be stored in the third semiconductor region; and
e) the first semiconductor region has at least one channel region which is situated in a current path between the two electrodes and, when a predetermined saturation current is reached between the two electrodes, is pinched off by depletion zones of said p-n junctions, after which the current is limited to a value below the saturation current.
This semiconductor configuration uses an advantageous combination of physical effects in the channel region to limit a current, particularly a short-circuit current, to an acceptable current value automatically and without active driving. In addition, the semiconductor configuration can, in principle, maintain this acceptable current value, on account of the charge storage in the electrically insulated third semiconductor region and the resultant continuous pinch-off of the channel region, even with subsequent voltage reductions at the two electrodes.
In accordance with an added feature of the invention, the second semiconductor region is formed inside the first semiconductor region below the contact region and projects beyond the contact region in all directions parallel to the surface of the first semiconductor region. This embodiment reaches particularly high breakdown strength.
The third semiconductor region preferably surrounds the contact region parallel to the first surface of the first semiconductor region.
In accordance with an additional feature of the invention, the second surface of the first semiconductor region is remote from and facing away from the first surface. This feature results in a vertical and thus particularly surge-proof design.
In accordance with another feature of the invention, the at least one contact region is one of a plurality of contact regions on the first surface. In other words, the first surface is preferably provided with a plurality of contact regions which, in particular, are allocated a common electrode.
In accordance with a further feature of the invention, a cohesive second semiconductor region is formed below the contact regions, and the cohesive second semiconductor region projects beyond all of the contact regions in all directions parallel to the first surface of the first semiconductor region.
The cohesive semiconductor region is preferably formed with openings through which further channel regions electrically connected in series with the aforementioned channel regions run in the first semiconductor region, preferably vertically. That is, in other words, the first semiconductor region has channel regions running through respective openings formed in the cohesive second semiconductor region, the channel regions being electrically connected in series, in the current path, with at least one respective channel region associated with the contact regions.
Alternatively, a respective associated second semiconductor region can be arranged below each contact region in the first semiconductor region, between which additional channel regions of the first semiconductor region run which are electrically connected, in the current path, in series with at least one, respectively, of the channel regions associated with the contact regions.
In accordance with again an added feature of the invention, an insulator region covers a surface of the third semiconductor region not adjoining the first semiconductor region. In that case, each third semiconductor region is covered by an insulator region on its surface not adjoining the first semiconductor region. The dielectric strength of the insulator region is preferably at least 20 V, in particular at least 50 V, between the first electrode and the third semiconductor region, and the electric breakdown field strength is preferably at least 5 MV/cm.
In accordance with again an additional feature of the invention, the semiconductor regions are formed from silicon carbide, and the insulator region is formed of silicon dioxide. More generally, the semiconductor used for the semiconductor configuration is preferably a semiconductor having an energy gap of at least 2 eV, which is distinguished by a low intrinsic charge carrier concentration (charge carrier concentration without doping), which in turn has a positive influence on the charge storage effect. The charge storage effect is particularly high if the semiconductor material provided for the semiconductor regions of the semiconductor configuration is silicon carbide (SiC), since SiC has an extremely low intrinsic charge carrier concentration. Further advantages of SiC are its high breakdown strength, high thermal resistance, chemical resistance and high thermal conductivity. Preferred polytypes of SiC are the 4H, 6H and 3C polytype. Preferred dopants for SiC are boron and aluminum for p-doping and nitrogen for n-doping. However, other semiconductors are also suitable, particularly silicon (Si).
Both with SiC and Si as the semiconductor, the insulator region used is preferably the dielectric silicon dioxide (SiO2). In a preferred embodiment, the silicon dioxide is grown thermally. Thermal oxide has excellent insulation properties. It is produced on SiC preferably by dry or wet oxidation at temperatures above 1000xc2x0 C., for example.
With the above and other objects in view there is provided, in accordance with the invention, a current limiter for limiting DC currents between a current source and an electrical consumer. The limiter device comprises the above-described semiconductor configuration with its first electrode electrically connected to the current source and the second electrode electrically connected to the consumer.
In a further development, there is also provided a current limiter for limiting AC currents between a current source and an electrical consumer. That device is formed by reverse-connecting in series two of the above-outlined semiconductor configurations between the current source and the consumer. Charge storage in the third semiconductor regions prevents the current from being repeatedly connected when the AC voltage changes polarity.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor configuration and current limiting device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.